1. Field of the Invention
The present invention relates to a semiconductor device for use, e.g., in high current applications, and also relates to a method of manufacture thereof.
2. Background Art
Japanese Laid-Open Patent Publication No. H07-273325 shows a cross-section of an IGBT (see FIG. 5 of this publication). This IGBT has a p-base region and guard rings, with the guard rings being formed to surround the periphery of the p-base region. A guard ring is a known breakdown voltage enhancing structure used to enhance the breakdown voltage of a semiconductor device.
In some semiconductor devices, a PN junction having a high degree of curvature is formed between an active region such as a base region through which the main current passes and the substrate, which may result in a decrease in the breakdown voltage of the device. In order to prevent this from occurring, it is desirable that a well region of the same conductivity type as the active region be formed in contact with the periphery of the active region. That is, the well region is formed between the active region and the adjacent breakdown voltage enhancing structure.
The active region and the well region typically have different impurity concentrations and different depths, since they have different functions, as described above. Therefore, the active region and the well region may be formed by separate ion implantation steps using different masks. That is, in order to form the active and well regions, the substrate may be ion-implanted twice. In such cases, the impurity-implanted region for forming the active region and that for forming the well region are formed to partially overlap each other thereby creating an implanted overlap region so that the active region will be fully in contact with the well region. It has been found, however, that in some cases the impurity concentration of the implanted overlap region becomes excessively high, with the result that the amount of holes implanted into the substrate is increased and that the recovery current flows primarily through the implanted overlap region, resulting in a decrease in the safe operating area (SOA) of the semiconductor device.